Author Correction: Hybrid CMOS-Memristor synapse circuits for implementing Ca ion-based plasticity model

Sci Rep. 2024 Sep 5;14(1):20719. doi: 10.1038/s41598-024-70848-y.

Jae Gwang Lim^{1

2}, Sung-Jae Park^{1

3}, Sang Min Lee^{1

3}, Yeonjoo Jeong¹, Jaewook Kim¹, Suyoun Lee¹, Jongkil Park¹, Gyu Weon Hwang¹, Kyeong-Seok Lee¹, Seongsik Park¹, Hyun Jae Jang¹, Byeong-Kwon Ju^{4

5}, Jong Keuk Park⁶, Inho Kim⁷

¹ Center for Semiconductor Technology, Korea Institute of Science and Technology, Seoul, 02792, South Korea.
² School of Electrical Engineering, Korea University, Seoul, 02841, South Korea.
³ Department of Micro/Nano Systems, Korea University, Seoul, 02841, South Korea.
⁴ School of Electrical Engineering, Korea University, Seoul, 02841, South Korea. bkju@korea.ac.kr.
⁵ Department of Micro/Nano Systems, Korea University, Seoul, 02841, South Korea. bkju@korea.ac.kr.
⁶ Center for Semiconductor Technology, Korea Institute of Science and Technology, Seoul, 02792, South Korea. jokepark@kist.re.kr.
⁷ Center for Semiconductor Technology, Korea Institute of Science and Technology, Seoul, 02792, South Korea. inhok@kist.re.kr.

No abstract available

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